BASIC PROCESSING UNIT

174 CHAPTER 5 • BASIC PROCESSING UNIT
IR_enable
Extend Immediate 2
MuxB and MuxINC
IR
Data
RZ PC MuxMA
MA_select
MEM read MEM_write
Sli
Address
Processor-memory interface
To cache and main memory
Figure 5.19 Processor-memory interface and IR control signals.
Multiplexers are controlled by signals that select which input data appear at the mul-tiplexer’s output. For example. when B_select is equal to O. MuxB selects the contents of register RB to be available at input InB of the ALU. Note that two bits are needed to control MuxC and MuxY, because each multiplexer selects one of three inputs. The operation performed by the ALU is determined by a k-bit control code. ALU_op, which can specify up to 2k distinct operations. such as Add, Subtract, AND, OR, and XOR. When an instruction calls for two values to be compared. a comparator performs the comparison specified, as mentioned earlier. The comparator generates condition signals that indicate the result of the comparison. These signals are examined by the control circuitry during the execution of conditional branch instructions to determine whether the branch condition is true or false. The interface between the processor and the memory and the control signals associated with the instruction register are presented in Figure 5.19. Two signals, MEM_read and MEM_write are used to initiate a memory Read or a memory Write operation. When the requested operation has been completed, the interface asserts the MFC signal. The instruction register has a control signal. IR_enable, which enables a new instruction to be loaded into the register. During a fetch step, it must be activated only after the MFC signal is asserted.